MARVELL 88E1512 DRIVER DOWNLOAD

Could you explain how to implement Xilinx provided patch at each these different steps? This has been tested on Zynq Ultrascale with a Daughter card. However, I don’t see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth1: Marvell PHYs products can also be combined with Marvell’s switching products for a complete networking solution. Thanks for the information. We have detected your current browser version is not the latest one.

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Careers at Marvell Marvell offers a collaborative fast-paced environment where innovative ideas can really make a difference. If they both operate at 3.

With the Alaska family, Marvell delivers a new class of Gigabit PHYs designed to meet the demands of next-generation green networks. Cadence GEM rev 0x at 0xec irq We have detected your current browser version is not the latest one. Hope this helps everyone with this problem I will post when I get the new release and test it. ChromeFirefoxInternet Explorer 11Safari.

Verified fix for this problem. We put our effort to fix this issue on hold, so I don’t have a solution for you.

Copyright c – Intel Corporation. As Ethernet technology becomes more prevalent in everyday mainstream applications such as IP phones, gaming consoles, PDAs, printers, and traditional home or corporate network connections, the demand for energy efficiency and advanced process technologies increases.

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Alaska Gigabit Ethernet PHYs Transceivers

We verified that before trying it in the kernel. Cadence GEM rev mmarvell at 0xeb irq We changed our HW definition to 88e1512 that a GPIO, and we take it out of reset in the early board init function of u-boot. Data Center and Cloud. However, eth1 still doesn’t work correctly. I have gotten a patch that looks like it applies to the Did you try running ping with u-boot?

The device tree in the newer kernels uses the MACB drivers. Marvll never comes up on eth1, although I can see received packets on the eth1 interface, as if the default PHY configuration is enough to receive packets in some form.

This particular PHY can only be configured for address zero or one, depending on how a couple of pins are strapped. Note that it assigns a different MAC address than is assinged in the device tree file.

Note that I am using two different sub-nets mmarvell the I have tried that previously and once againt to verify.

Reluctant to pursue it as we are not using Petalinux:.

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We have a custom board with a Zynq using two Marvell 88e PHYs for dual ethernet and have not been able to get eth1 up and running on xilinx-linux eth0 works fine. The software doesn’t seem to do anything with it. Product Brief Technical Product Brief. Product Selector Guide Access comprehensive product specifications for Marvell’s family of Transceivers products: What other kernel settings did you have to enable to allow the Marvell 88e PHY to have the correct drivers from petalinux?

PHY Transceivers, Alaska X Gigabit Ethernet PHY – Products – Marvell

Add mdio in the top level: Thanks for the information. Oddly, eth1 seems to receive packets even though the link is never marvekl. I’m looking for some insight that I’m missing, or some other clue to indicate why the kernel drivers can’t detect PHY1 at address 1 correctly. I Have met the same problem, hope could get some ideas from you!